Projects

Requirement: Perform a matrix multiplication of two randomly generated floating-point square (I generalized it to any arbitrary size) matrices, then find the two minimum values and their indices in the product matrix, with sequential C/C++, ISPC (with multi-task), Pthread (with ISPC), OpenMP (with ISPC), 1/2 GPU CUDA, 4 GPU CUDA with MPI
- Challenge 1: Maximize parallelization of minimum searching in each subroutine (ISPC instance/Pthread/OpenMP thread/CUDA thread block), instead of reducing it sequentially in the main route.
- Challenge 2: Atomic update of both minimum value and index
I took cache (locality and false sharing), SIMD/thread/task/SIMT parallelism into consideration achieving the following result, compared with naive Sequential C:
- ISPC with multi-task: 199×
- Pthread/OpenMP with ISPC: 259×
- 2-GPU CUDA: 16388×
- 4-GPU CUDA MPI: 667×
Specifically, my CUDA program achieved 80% - 85% of cuBLAS’s performance on matrices of order 2k, 4k, 8k
- Hierarchy: Device level, Thread Block level, Warp level, Thread level
- Vectorized load, Bank conflict, Coalesced memory access
- Double buffering
- Works on arbitrary sizes
Archived as an example of an outstanding ESE 565 project

Image source: Strassen’s Algorithm Reloaded on GPUs

Background: VM live migration is a widely utilized technique in data centers for system upgrade, load balancing, etc. Existing VM live migration leverages TCP/IP or RDMA as its underlying data transmission channel, inevitably having a data copy at the dst side, which is widely deemed as a price that must be paid.
However, this axiom-like assumption is now overturned by hardware memory pooling, provided by commodity-ready Compute Express Link (CXL) 2.0.
Mohit and I implemented a working proof-of-concept prototype on emulated CXL hardware, achieving a 2× faster migration speed over traditional TCP-based methods in internal benchmarks
We both helped implement QEMU-level CXL tiering solution
- Only hot pages are transferred
- Cold pages are remapped rather than migrated
- Zero-copy by definition
Image source: Compute Express Link™ 2.0 Specification: Memory Pooling

Stony Brook University, Advisor: Prof. Michael Ferdman

Implemented full TX/RX paths from scratch (900+ lines of clean, well-documented Linux kernel code), supporting:
- Multi-fragment TX transmission
- In-place RX reception
- NAPI-based polling
Explored bonded network interfaces to improve throughput and scalability, including:
- Link aggregation with round-robin and balance-xor modes
- IRQ CPU affinity tuning via smp_affinity for improved parallelism
Achievements:
- Achieved 50% throughput improvement over the previous generation under the iperf3 benchmark
- We are the first students in the past 5 years to actually deliver a steady and high-performance driver
- It has been running smoothly and bug-free for over six months, reliably serving as core infrastructure for the COMPAS lab — something its predecessor had NEVER achieved.

Huawei Technologies Co., Ltd, Advisor: Dr. Yunfei Du, Tuo Fang, Dr. Yuxin Ren, Prof. Guyue (Grace) Liu

OpenUCX is an open-source, production-grade communication framework for data-centric and high-performance applications.
Helped implement XRC service type, efficiently bringing down QP numbers thus increasing RDMA scalability
Helped resolve the Head-of-Line blocking problem with a simple yet effective two-level message slicing policy
Helped set up a finer credit-based flow control mechanism
Evaluated our implementation based on both micro-benchmarks and real-world applications
Our work has been recognized and the paper has been accepted to EuroSys’26

Background: To meet the need for more memory from HPC and database applications, our lab researched into tiered memory systems, where ideally we exploit a fast DRAM tier for performance and a slow SSD/NVM tier for capacity.
However such systems need tuning and clever data placement strategies to avoid severe application performance penalty. etmem, is Huawei’s tiered memory system manager. It takes a traditional approach of access bit checking and watermark comparison to determine the temperature of a page.
Compute Express Link (CXL) is a new CPU to peripheral interconnect. With its CXL.mem subprotocol, CPUs are able to access CXL memory as cacheable system memory. With access latency comparable to that of a remote NUMA node (~100ns for 64B read), it has been one of the most promising emerging memory extent spotted these years.
I observed the frequent page ping-pong caused by original, coarse-grained access bit checking method, and developed a substitute kernel module that multiplexed the original etmem workflow, selectively listening to either access bit checking or fine-grained hardware access counter results.

Image source: TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory